The TTEDevelopment System A664 supporting the ARINC 653 interface is an out-of-the box starter kit for integrating TTEthernet®’s deterministic network technology with the time and space partitioned real-time operating system VxWorks 653. The easy-to-use and ready-to-run solution includes hardware and software as well as a Distributed IMA demo application showing deterministic communication among the different real-time operation system partitions. The system supports up to 1 Gbit/s speed, enables event-driven Ethernet (IEEE 802.3) as well as rate-constrained (ARINC 664 part 7) and hard real-time (Time-Triggered Ethernet SAE AS6802) communication on the same network with the option to synchronize IMA modules using the fault-tolerant TTEthernet network time base.
Distributed Integrated Modular Avionics
Time and space partitioning is the cornerstone of Integrated Modular Avionics (IMA). It supports the integration of various functions of different criticality on one module to reduce the number of control modules and simplify certification and upgrades. Distributed IMA (DIMA) is an extended IMA architecture utilizing deterministic, high-integrity communication bandwidth partitioning as described in RTCA DO-297.
TTEthernet and DIMA
Robust partitioned communication with µs-jitter and distributed fault-tolerant synchronization is ensured by TTEthernet. The whole networked system becomes a distributed, fault-tolerant, hard real-time computer, capable of handling multiple distributed functions of different criticality in one network. This means that both critical and non-critical applications can safely be executed on one integrated ARINC 653 system.
Key benefits
Using TTEthernet® as an open real-time Ethernet communication platform for Distributed Integrated Modular Avionics (DIMA) has several benefits. For example it can be avoided that the hundreds of different distributed applications and functions on a shared resource clash with each other or block resources. For instance if network data for a critical function cannot be received before the computing deadline the function gets delayed until the next computing cycle which could be catastrophic for the entire system. This scenario can be avoided when using TTEthernet for DIMA. Simulating such a scenario and others are benefits of the development system. Further benefits of the TTEDevelopment System supporting the ARINC 653 interface include, but are not limited to:
- An easy-to-use and ready-to-run solution including hardware and software as well as a Distributed IMA demo application
- Ideal solution to evaluate a strictly deterministic system design using the highly precise (sub microsecond) fault-tolerant time base of TTEthernet for synchronizing modules/partitions in DIMA architectures
- Robust time and address space partitioning according to standards (e.g. ARINC 653)
- Can be integrated in different operating systems on the market (portable source codes) without changes/modifications of any OS/standard interfaces.
- Re-use of existing communication mechanisms (e.g. sampled/queued ports in ARINC 653) as interface for message exchange
- Seamless integration of already existing IMA applications without modifications is feasible
- Deterministic high bandwidth, low latency and minimal jitter communication up to the application level
- Three supported Ethernet traffic classes on one Ethernet network i.e. standard Ethernet (IEEE 802.3), rate-constrained (ARINC 664 part 7) and time-triggered (SAE AS6802)
Key features
- Using highly precise fault-tolerant time base for synchronization of DIMA architectures
- The whole networked system becomes a distributed, fault-tolerant, hard real-time computer, capable of handling multiple distributed functions of different criticality in one network
- Robust partitioned communication with µs-jitter and distributed fault-tolerant synchronization is ensured by TTEthernet
- An optional oscilloscope allows tracking and measurements of synchronization among partitions
- Inherent support for safety and redundancy at the network level without application modification
- Scalable fault-tolerance (no, single, or double fault-tolerance)
- Built-in fault-tolerant clock synchronization protocol
- Robust partitioning among different traffic classes (time-triggered, rate-constrained, best-effort traffic)
- The entire system offers a deterministic, high bandwidth, low latency and minimal jitter communication from the network level up to the application level
- Convergence of rate-constrained (ARINC 664 part 7) , hard real-time (SAE AS6802) and standard event-driven Ethernet traffic (IEEE 802.3) in parallel on the same network
- 48 ports with up to 1 Gbit/s full-duplex enable 31,2 Gbit/s full wire-speed performance (two 24 port switches with each 6x 1 Gbit/s and 18x 10/100 Mbit/s speeds)
- Bandwidth efficiency while maintaining full determinism (up to 95% utilization of available network bandwidth)
- Robust time and address space partitioning according to standards (e.g. ARINC 653)
- No change/modification of any OS/standard interfaces
- Re-use of existing communication mechanisms (e.g. sampled/queued ports in ARINC 653) as interface for message exchange
- Seamless integration of already existing IMA applications without modifications is feasible
- Wind River VxWorks 653 v2.4 for Creative Electronic Systems' SBC RIO6-8093TF & SBC RIO6-8093AF
- Other RTOS and SBC combinations on request